Chemical Mechanical Polishing (CMP)

With diminishing size and increasing efficiency of electronic devices, there has been tremendous pressure for micro-chip designers to achieve more planarized surfaces to reduce defects in fabrication. CMP is a process for polishing wafers to the nanometer and even sub nanometer range, in the hopes of achieving a more planar foundation upon which to build a circuit. However The complexity of CMP physics which includes abrasive wear, chemical wear, fluid dynamics, particle dynamics, is still largely misunderstood.

The PFTL currently performs experiments and modeling in order to understand the dominant physical interactions in the process. The final aim of this work is to develop an all-encompassing predictive framework that can help chip designers account for the limitations of the manufacturing process in their circuit design.